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Ordering number : EN5996
CMOS IC
LC662104A, 662106A, 662108A
Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM
Overview
The LC662104A, LC662106A, and LC662108A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a special-purpose telephone controller, including ROM, RAM, I/O ports, a serial interface, a DTMF generator, timers, and interrupt functions. These microcontrollers are available in a 30-pin package.
Features and Functions
* On-chip ROM capacities of 4, 6, and 8 kilobytes, and an on-chip RAM capacity of 384 x 4 bits. * Fully supports the LC66000 Series common instruction set (128 instructions). (The special-purpose instructions for TM1 and SI/01 are disabled.) * I/O ports: 24 pins * DTMF generator This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output. * 8-bit serial interface: one circuit
* Instruction cycle time: 0.95 to 10 s (at 3.0 to 5.5 V) * Powerful timer functions and prescalers -- Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. -- Time base function using a 12-bit prescaler. * Powerful interrupt system with 6 interrupt factors and 6 interrupt vector locations. -- External interrupts: 3 factors/3 vector locations -- Internal interrupts: 3 factors/3 vector locations * Flexible I/O functions Selectable options include 20-mA drive outputs, pull-up and open drain circuits. * Optional runaway detection function (watchdog timer) * 8-bit I/O functions * Power saving functions using halt and hold modes. * Packages: DIP30SD, MFP30S * Evaluation ICs: LC665099 (evaluation chip) + EVA86K - ECB662500 LC66E2108(on-chip EPROM microcontroller)
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
101698RM (OT) No. 5966-1/13
LC662104A, 662106A, 662108A
Package Dimensions
unit: mm 3196-DIP30SD
[LC662104A]
unit: mm 3216-MFP30S
[LC662106A]
SANYO: DIP30SD
SANYO: MFP30S
Type No. LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B/562B/566B LC66354C/356C/358C LC662104A/06A/08A LC662304A/06A/08A/12A/16A LC662508A/12A/16A LC665304A/06A/08A/12A/16A LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 LC66E2108 LC66E2316 LC66E2516 LC66E5316 LC66P2108 LC66P2316 LC66P2516 LC66P5316
No. of pins 42 42 64 42 42 64 42 64 42 30 42 64 48 42 42 42 42 64 64 30 42 64 52/48 30 42 64 48
ROM capacity 4 K/6 K/8 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 4 K/6 K/8 KB
RAM capacity 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 384 W DIP64S DIP42S DIP64S DIP42S DIP30SD DIP42S DIP64S DIP48S DIP42S DIP42S DIP64S DIP42S
Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP48E MFP30S QFP48E QFP64E QFP48E QFC48 with window QFP48E QFC48 with window QFP48E QFC64 with window QFP64E
Features
Normal versions 4.0 to 6.0 V/0.92 s
Low-voltage versions 2.2 to 5.5 V/3.92 s Low-voltage high-speed versions 3.0 to 5.5 V/0.92 s 2.5 to 5.5 V/0.92 s On-chip DTMF generator versions 3.0 to 5.5 V/0.95 s Dual oscillator support 3.0 to 5.5 V/0.95 s
4 K/6 K/8 K/12 K/16 KB 512 W 8 K/12 K/16 KB 512 W
4 K/6 K/8 K/12 K/16 KB 512 W EPROM 8 KB OTPROM 8 KB EPROM 8 KB OTPROM 8 KB EPROM 16 KB OTPROM 16 KB EPROM 8 KB EPROM 16 KB EPROM 16 KB EPROM 16 KB OTPROM 8 KB OTPROM 16 KB OTPROM 16 KB OTPROM 16 KB 512 W 512 W 512 W 512 W 512 W 512 W 384 W 512 W 512 W 512 W 384 W 512 W 512 W 512 W
DIC42S with window DIP42S DIC42S with window DIP42S DIC64S with window DIP64S
Window and OTP evaluation versions 4.5 to 5.5 V/0.92 s
DIC42S with window DIC64S with window DIC52S with window DIP30SD DIP42S DIP64S DIP48S
QFC48 with window QFC64 with window QFC48 with window MFP30S QFP48E QFP64E QFP48E
Window evaluation versions 4.5 to 5.5 V/0.95 s
OTP 4.0 to 5.5 V/0.95 s
No. 5996-2/13
LC662104A, 662106A, 662108A
We recommend the use of reflow-soldering techniques to solder-mount MFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).
No. 5996-3/13
LC662104A, 662106A, 662108A System Block Diagram
Differences between the LC663XX Series and the LC6621XX Series
Item System differences * Hardware wait time (number of cycles) when hold mode is cleared LC6630X Series (Including the LC66599 evaluation chip) 65536 cycles About 64 ms at 4 MHz (Tcyc = 1 s) LC6635XB Series 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 s) LC6621XX Series 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 s)
* Value of timer 0 after a reset (Including the value after hold mode Set to FF0. is cleared) * DTMF generator * Inverter array * SIO1 * Three-value inputs/comparator inputs * Three-state output from P31 and P32 * Using P0 to clear halt mode * External extended interrupts None (Tools are handled with external devices.) None (Tools are handled with external devices.) Yes Yes None In 4-bit groups None for INT3, INT4, and INT5. (Tools are handled with external devices.) Shared with INT2 (Tools are handled with external devices.) * LC66304A/306A/308A 4.0 to 6.0 V/0.92 to 10 s * LC66E308/P308 4.5 to 5.5 V/0.92 to 10 s P0, P1, P4, and P5: about 3 to 10 k * P2 to P6 and PC: 15V handling * P0, P1, PD, PE: Normal voltage handling
Set to FFC.
Set to FFC.
None None Yes Yes None In 4-bit groups None for INT3, INT4, and INT5.
Yes None None None Yes Can be specified for each bit. INT3, INT4, and INT5 can be used with the internal functions.
* Other P53 functions
Shared with INT2 * 3.0 to 5.5 V/0.92 to 10 s * LC6635XA 2.2 to 5.5 V/3.92 to 10 s 3.0 to 5.5 V/1.96 to 10 s
Shared with INT2
Differences in main characteristics * Operating power-supply voltage and operating speed (cycle time) * Pull-up resistors * Port voltage handling
3.0 to 5.5 V/0.95 to 10 s
P0, P1, P4, and P5: about 3 to 10 k P0, P1, P4, and P5: about 100 k * P2 to P6 and PC: 15V handling * P0, P1, PD, PE: Normal voltage handling P2 to P4, P51, and P53: 15V voltage handling Others: normal voltage handling
No. 5996-4/13
LC662104A, 662106A, 662108A Pin Function Overview
Pin I/O Overview Output driver type Options State after a reset
P00 P01 P02 P03
I/O
I/O ports P00 to P03 * Input or output in 4-bit or 1-bit units * P00 to P03 support the halt mode control function (This function can be specified in bit units.)
* Pch: Pull-up MOS type * Nch: Intermediate sink current type
* Pull-up MOS or Nch OD output * Output level on reset
High or low (option)
P10 P11 P12 P13
I/O
I/O ports P10 to P13 Input or output in 4-bit or 1-bit units
* Pch: Pull-up MOS type * Nch: Intermediate sink current type
* Pull-up MOS or Nch OD output * Output level on reset
High or low (option)
P20/SI0 P21/SO0 P22/SCK0 P23/INT0
I/O
I/O ports P20 to P23 * Input or output in 4-bit or 1-bit units * P20 is also used as the serial input SI0 pin. * P21 is also used as the serial output SO0 pin. * P22 is also used as the serial clock SCK0 pin. * P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input.
* Pch: CMOS type * Nch: Intermediate sink current type * Nch: +15V handling when OD option selected
CMOS or Nch OD output
H
P30/INT1 P31/POUT0 P32
I/O
I/O ports P30 to P32 * Input or output in 3-bit or 1-bit units * P30 is also used as the INT1 interrupt request. * P31 is also used for the square wave output from timer 0. * P31 and P32 also support 3-state outputs.
* Pch: CMOS type * Nch: Intermediate sink current type * Nch: +15V handling when OD option selected
CMOS or Nch OD output
H
P33/HOLD
I
Hold mode control input * Hold mode is set up by the HOLD instruction when HOLD is low. * In hold mode, the CPU is restarted by setting HOLD to the high level. * This pin can be used as input port P33 along with P30 to P32. * When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied.
P40 P41 P42 P43
I/O
I/O ports P40 to P43 * Input or output in 4-bit or 1-bit units * Input or output in 8-bit units when used in conjunction with P50 to P53. * Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53.
* Pch: Pull-up MOS type * Nch: Intermediate sink current type * Nch: +15V handkling when OD option selected
* Pull-up MOS or Nch OD output * Output level on reset
High or low (option)
Continued on next page.
No. 5996-5/13
LC662104A, 662106A, 662108A
Continued from preceding page.
Pin I/O Overview Output driver type Options * Pull-up MOS or Nch OD output * Output level on reset * Output level after a reset (An external pull-up resistor must be supplied when used for DT output.) State after a reset
P50 P51/DP P52/DT P53/INT2
I/O
I/O ports P50 to P53 * Input or output in 4-bit or 1-bit units * P51 is also used for dial pulse output * P52 is also used for DTMF output * P53 is also used as the INT2 interrupt request.
* Pch: Pull-up MOS type * Nch: Intermediate sink current type * Nch: +15-V handling when OD option selected (P51 and P53 only)
High or low (option)
OSC1 OSC2
I O
System clock oscillator connections When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. CPU test pin This pin must be connected to VSS during normal operation. Power supply pins
Ceramic oscillator or external clock selection
Option selection
RES
I
TEST
I
VDD VSS
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output.
No. 5996-6/13
LC662104A, 662106A, 662108A User Options 1. Port 0, 1, 4, and 5 output level options a reset The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following two options.
Option Output high at reset Output low at reset Conditions and notes The four bits of ports 0, 1, 4, or 5 are set in a group The four bits of ports 0, 1, 4, or 5 are set in a group
2. Oscillator circuit options * Main clock
Option Circuit Conditions and notes
External clock
OSC1
The input has Schmitt characteristics
C1
Ceramic oscillator Ceramic oscillator
OSC1
C2
OSC2
Note: There is no RC oscillator option.
3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option. 4. Port output type options * The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, and P5 can be selected individually from the following two options.
Option Circuit Output data Open-drain output Input data The port P2, P3, P5, and P6 inputs have Schmitt characteristics. Conditions and notes
DSB
Output data Output with built-in pull-up resistor
The port P2, P3, and P5 inputs have Schmitt characteristics. The CMOS outputs (ports P2 and P3) and the pull-up MOS outputs (P0, P1, P4, and P5) are distinguished by the drive capacity of the pchannel transistor.
Input data
DSB
No. 5996-7/13
LC662104A, 662106A, 662108A LC662108 Series Option Data Area and Definitions
ROM area Bit 7 6 5 2000H 4 3 2 1 0 7 6 5 2001H 4 3 2 1 0 7 6 5 2002H 4 3 2 1 0 7 6 5 2003H 4 3 2 1 0 7 6 2004H to 200CH 5 4 3 2 1 0 7 6 5 200DH 4 3 2 1 0 7 6 5 200EH 4 3 2 1 0 Reserved. Must be set to predefined values. This data is generated by the assmbler (0x). If the assembler is not used, set this data to 00. Reserved. Must be set to predefined values. This data is generated by the assmbler (21). If the assembler is not used, set this data to 00. Unused This bit must be set to 0. *: Location 2008H must be set to 7F. P5 P4 Unused Oscillator option Unused P1 P0 Output level at reset Option specified Output level at reset Option/data relationship 0 = high level, 1 = low level This bit must be set to 0. 0 = (RC oscillator) external clock, 1 = ceramic oscillator This bit must be set to 0. 0 = low level, 1 = high level 0 = none, 1 = yes
Watchdog timer option P13 P12 P11 P10 P03 P02 P01 P00 Unused P32 P31 P30 P23 P22 P21 P20 P53 P52 P51 P50 P43 P42 P41 P40 Output type Output type Output type Output type Output type Output type
0 = OD, 1 = PU
0 = OD, 1 = PU
This bit must be set to 0.
0 = OD, 1 = PU
0 = OD, 1 = PU
0 = OD, 1 = PU
0 = OD, 1 = PU
Continued on next page. No. 5996-8/13
LC662104A, 662106A, 662108A
Continued from preceding page.
ROM area Bit 7 6 5 200FH 4 3 2 1 0 Reserved. Must be set to predefined values. This data is generated by the assmbler (00). If the assembler is not used, set this data to (00). Option specified Option/data relationship
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 ION1 Output current per pin -IOP1 -IOP2 ION1 Total pin current ION2 IOP1 IOP2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD P2, P3 (except for the P33/HOLD pin), P4, P51, and P53 All other inputs P2 and P3 (except for the P33/HOLD pin) All other inputs P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5 P0, P1, P4, P5 P2, P3 (except for the P33/HOLD pin) P1, P2, P3 (except for the P33/HOLD pin) P0, P4, P5 P1, P2, P3 (except for the P33/HOLD pin) P0, P4, P5 Ta = -30 to +70C: DIP30S (MFP30S) Conditions Ratings -0.3 to +7.0 -0.3 to +15.0 -0.3 to VDD + 0.3 -0.3 to +15.0 -0.3 to VDD + 0.3 20 2 4 75 75 25 25 340 (200) -30 to +70 -55 to +125 Unit V V V V V mA mA mA mA mA mA mA mW C C 1 2 1 2 3 4 4 3 3 4 4 5 Note
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. Sink current 4. Source current 5. We recommend the use of reflow soldering techniques to solder mount MFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).
No. 5996-9/13
LC662104A, 662106A, 662108A Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified.
Parameter Operating supply voltage Memory retention supply voltage Symbol VDD VDDH VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Operating frequency (instruction cycle time) [External clock input conditions] fop (Tcyc) VDD VDD: During hold mode P2, P3 (except for the P33/HOLD pin), P4, P51, and P53: N-channel output transistor off P33/HOLD, RES, OSC1: N-channel output transistor off P0, P1, P50, P52: N-channel output transistor off P2, P3 (except for the P33/HOLD pin), RES, and OSC1: N-channel output transistor off P33/HOLD: VDD = 1.8 to 5.5 V P0, P1, P4, P5, TEST: N-channel output transistor off Conditions min 3.0 1.8 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS 0.4 (10) Ratings typ max 5.5 5.5 13.5 VDD VDD 0.2 VDD 0.2 VDD 0.2 VDD 4.20 (0.95) Unit V V V V V V V V MHz (s) 2 1 Note
Frequency
fext
0.4
4.20
MHz
Pulse width
textH, textL
OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.)
100
ns
Rise and fall times
textR, textF
30
ns
Note: 1. Applies to pins with open-drain specifications. However, VIH2 is applied to the P33/HOLD pin. When ports P2 and P3 have CMOS output specifications they cannot be used as input pins. 2. Applies to pins with open-drain specifications.
No. 5996-10/13
LC662104A, 662106A, 662108A Electrical Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.
Parameter Symbol Conditions P2, P3 (except for the P33/HOLD pin), P4, P51, and P53: VIN = 13.5 V, with the output Nch transistor off P0, P1, P50, P52, OSC1, RES, and P33/HOLD: VIN = VDD, with the output Nch transistor off P0, P1, P2, P3, P4, and P5: VIN = VSS, with the output Nch transistor off P2, P3 (except for the P33/HOLD pin) P0, P1, P4, P5 P0, P1, P2, P3, P4, and P5 (except for the P33/HOLD pin): IOL = 1.6 mA P0, P1, P2, P3, P4, and P5 (except for the P33/HOLD pin): IOL = 8 mA P2, P3, P4, P51, and P53: VIN = 13.5 V Does not apply to P2, P3, P4, P51, and P53: VIN = VDD 0.1 VDD P2, P3, P4, P5, and RES 0.5 VDD 0.2 VDD OSC1, OSC2: See Figure 2. 4 MHz See Figure 3. 4 MHz 4.0 10.0 0.8 VDD 0.5 VDD V V IOH = -1 mA IOH = -0.1 mA -1.0 VDD - 1.0 VDD - 0.5 30 100 150 0.4 1.5 5.0 1.0 min Ratings typ max 5.0 Unit Note
IIH1 Input high-level current IIH2 Input low-level current Output high-level voltage Value of the output pull-up resistor IIL1 VOH1 RPO VOL1 Output low-level voltage VOL2 IOFF1 Output off leakage current [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF fCF fCFS VHYS VtH VtL IOFF2
A
1
1.0
A A V k V V A A
1 2 3
5
6 6
MHz ms
0.9 2.0 SCK0: With the timing of Figure 4 and the test load of Figure 5. 0.4 1.0 0.1
s Tcyc s Tcyc s
Low-level and high-level Input pulse widths Output Rise an fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time [Pulse conditions] Output
tICK tCKI
SI0: With the timing of Figure 4. Stipulated with respect to the rising edge () of SCK0.
0.3 0.3
s s
tCKO
SO0: With the timing of Figure 4 and the test load of Figure 5. Stipulated with respect to the falling edge () of SCK0.
0.3
s
INT0 high and low-level
tIOH, tIOL
INT0: Figure 6, conditions under which the INT0 interrupt can be accepted, conditions under which the timer 0 event counter or pulse width measurement input can be accepted INT1, INT2: Figure 6, conditions under which the corresponding interrupt can be accepted RES: Figure 6, conditions under which reset can be applied.
2
Tcyc
High and low-level pulse widths for interrupt inputs other than INT0 RES high and low-level pulse widths
tIIH, tIIL tRSH, tRSL
2 3
Tcyc Tcyc
Operating current drain
IDD OP IDDHALT IDDHOLD
VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: VDD = 1.8 to 5.5 V
4.5 4.5 2.5 2.5 0.01
8.0 8.0 5.5 5.5 10
mA mA mA mA A
8
Halt mode current drain Hold mode current drain
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. 4. With the output Nch transistor off for pull-up output specification pins. 6. With the output Pch transistor off for open-drain output specification pins. 7. Reset state
No. 5996-11/13
LC662104A, 662106A, 662108A Tone (DTMF) Output Characteristics DC Characteristics at Ta = -30 to +70C, VSS = 0 V
Parameter Tone output voltage Row/column tone output voltage ratio Symbol VT1 DBCR1 Conditions DT: Single tone, VDD = 3.5 to 5.5 V* DT: Dual tones, VDD = 3.5 to 5.5 V* min 0.9 1.0 Ratings typ 1.3 2.0 max 2.0 3.0 Unit Vp-p dB
Note*:
See Figure 7.
VDD 0.8 VDD 0.2 VDD VSS
External clock
OSC1
(OSC2) Open textF textL textR 1/fext textH
Figure 1 External Clock Input Waveform
OSC1
OSC2 C2
Oscillator unstable period tCFS
Operating VDD lower limit 0V
C1
Ceramic oscillator
Stable oscillation
Figure 2 Ceramic Oscillator Circuit Table 1 Recomended Ceramic Oscillator Constants
External capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG 4 MHz (Kyocera Corporation) KBR4.0MSB C1 = 33 pF C2 = 33 pF C1 = 33 pF C2 = 33 pF
Figure 3 Oscillator Stabilization Period
Built-in capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CST4.00MG 4 MHz (Kyocera Corporation) KBR4.0MKC
tCKCY tCKL SCK0 0.2 VDD (input) 0.4 VDD (output) SI0 tCKR tCKH tCKF 0.8 VDD (input) VDD - 1 (output) tICK tCKI 0.8 VDD 0.2 VDD tCK0 SO0 VDD - 1 0.4 VDD
Figure 4 Serial I/O Timing Timing Load
Figure 5
No. 5996-12/13
LC662104A, 662106A, 662108A
tI0H tI1H tRSH 0.8 VDD 0.2 VDD tI0L tI1L tPINL tRSL
Figure 6 Input Timing for the INT0, INT1, INT2, and RES pins
Figure 7 Tone Output Pin Load
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject to change without notice. PS No. 5996-13/13

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